Increasing the number of sensitive pixels in an instrument is a classical way to improve its observational capabilities. From cosmology, in the millimeter wave range, to high-energy astrophysics space instruments, the readout of thousands of cryogenic detectors requires dedicated electronic developments. Application-specific integrated circuits - ASICs offer major advantages in this context : specific design, small size and optimized performances. The development of low-noise integrated circuits, for cryogenic detection chains, is an important expertise of the APC laboratory; recognized in an international context, mainly through the QUBIC, ATHENA X-IFU and the CMB S4 instruments. ASIC development is one of the key fields of research to meet the increasing performance requirements of new generation instruments. These developments have also to follow the evolution of integrated circuit fabrication technologies down to deep-sub micron processes. 
 
In this context, we proposed a PhD subject based on the sensitivity improvement of large array of superconducting detectors readouts; focussing on the room temperature front-end readout and control of cryogenic sensors.
 
A low-noise front-end readout is usually composed of an amplifier and a shaper, followed by a digitizer (analog-to-digital converter - ADC) more or less far from the front-end electronics. Moreover, adjustable ultra-low-noise biasing of detectors and other cryogenic devices (performed via digital-to-analog converters - DACs) can also have a major impact on the detection chain performances (in terms of noise and drift). Several other functions (feedback, calibration, offset correction, buffers, etc.) can also be integrated, leading to very optimized specific electronics. Some of these functions are purely analog (amplifier, current reference), others mixed (DAC, ADC), and finally, some digital functions, namely for the communication buses to DAC and ADC, are only digital. Most of these functions have to be integrated into a single ASIC to maximize integration, and remain efficient, in a thermal and ionizing space environment.
 
One important aspect of the development of ultra low noise front-end electronics is flicker noise. Indeed, both for background measurements, as for example CMB detection, or for the readout of time domain multiplexed signals, the low-frequency noise is a significant contamination of the scientific signals. Moreover, from an ASIC designer’s point of view, low frequency noise is not a well-predictable parameter. Indeed, compared to fundamental Johnson or shot noises, which are easy to quantify, flicker noise is an empirical parameter highly dependent on the technology and the fabrication process. It is also difficult to measure it at very low frequency; and it is mixed with other contributions, such as low frequency biasing fluctuation (hard to filter) and thermal drifts. Anyway, Flicker noise can be mitigated using bipolar technology, by reducing the biasing, and/or by increasing the surface area of the active devices. Anyway, trade-offs with white noise and cut-off frequency have to be also considered in these choices.
 
We propose a PhD subject based on a systematic analysis of the impact of flicker noise in cryogenic detection chains used for CMB or X-Ray observations; And how to minimize it using micro-electronic technology for front-end readout and biasing of a superconducting SQUID/TES detection chain. 



·       We will first consider BiCMOS SiGe technologies and will concentrate on differential low-noise and low-gain-drift amplifiers (LNA) with 160 V/V gain and a bandwidth from DC to more than 20 MHz (Gain x Bandwidth > 3 GHz). A low-noise differential offset compensation will be also included in the LNA.
·       Low-capacitance, low-noise and low-drift adjustable current sources to bias SQUID and TES in the milliamps range will be also studied to minimize low-frequency noise down to a few 10 pA/√Hz at 1 Hz. 
·       Ultra-sensitive on-chip thermometer (>10 µA/K) with offset nulling and differential output currents will be studied to distinguish thermal drift contamination from low frequency noise.
 
Very low 1/f noise integrated readout circuits with on-chip sensitive thermometers are major challenges for onboard astronomical applications. The study of flicker noise considerations to the ASIC design will improve the robustness and reliability of the space instruments to which the APC contributes. These challenges, therefore, constitute a rich and ambitious instrumental thesis subject that fits perfectly into the perspectives of instrument developments of the APC laboratory, in particular within the framework of the development of the readout chain of the X-IFU instrument for the ATHENA space mission. This activity will be supported by an existing team already involved in cryogenic detection chain developpement. Furthermore the APC applications, these are also innovative subjects that meet current needs in the general field of microelectronics. The PhD student needs strong skills in electronics, microelectronics and controlled systems. He/She will first establish a state of the art of low-frequency noise in ASIC and “on-chip” thermometry techniques. For simulations and circuit design, he/she will use Cadence Virtuoso CAD tools. So, it is assumed that he/she has already had initial training on these tools. The BiCMOS SiGe ST 130 nm technology will be preferred, yet other technologies such as IHP could be considered. One to two runs of ASIC are expected during the thesis. The handling and adaptation of a noise and thermal test bench have also to be considered. Participation in a radiation test campaign in a cyclotron is also planned to study the impact of radiation on the 1/f noise performances. The results will lead to publications in international peer-reviewed journals.