Hardening of low-noise readout integrated circuits for space thermal and ionizing environment - fine on-chip thermometry & quiet triple voting


Enlarge the number of sensitive pixels put in an instrument is a classical way to improve observatories. From cosmology in the millimeter range to high-energy astrophysics space instruments, the readout of thousands of cryogenic detectors requires dedicated electronic developments. Application-Specific Integrated Circuits - ASICs offer major advantages in this context: specific design, small size and optimized performances. In addition, consumption is kept to a minimum, and the hardening by design can protect against the effects of radiation and thermal drifts faced in space. The development of low-noise integrated circuits, for cryogenic detection chains, is an important APC laboratory know-how; recognized in an international context, mainly through the QUBIC and ATHENA X-IFU instruments. ASIC developments are one of the visible fields of research to meet ever more ambitious needs. These developments have also to follow accessible integrated circuit technologies evolution. Last, constraints linked to the space environment are a main concern for most of our involvements.
Low-noise readout is usually composed of amplifier and shaper, followed by a digitizer (Analog-to-Digital Converter - ADC) more or less far from the front-end. Moreover, trimmer or adjustable biasing (Digital-to-Analog Converter - DAC) can also have a major impact on the detection chain performances (in terms of noise and stability). Many other functions (feedback, calibration, offset correction, buffers, etc.) can also be integrated. Some of these functions are purely analog (amplifier, current reference), other mixed (DAC, ADC), finally some digital functions, namely for the communication buses to DAC and ADC, are only digital. Most of these functions have to be integrated into a single ASIC to maximize integration, and remain efficient, in a thermal and ionizing space environment.
In spacecraft, all subsystems are monitored in temperature. For ASICs, precise and constant monitoring of the chip temperature is a crucial indicator to compensate for thermal drifts. Likewise, in satellites, it is common to redundant most of the important on-board sub-systems. For ASICs, Triple Modular Redundancy (TMR) with Self-Restoring Logic (SRL) has to be implemented on registers. In this context, we propose a PhD subject that can address these two aspects:
  • Fine, on-chip, thermometry, with no common-mode coupling: this first part, mainly analog, will focus on CMOS and BiCMOS circuits allowing temperature measurements to monitor and correct thermal drifts. Thermometry based on the thermal dependencies of the “threshold voltage” of junctions is commonly used for ASIC thermometry. The discussed PhD subject is interested in the optimization of the sensitivity of a thermometer on silicon, with in particular the correction of offset around room temperature, and the propagation of a differential signal allowing it to be read out without common-mode coupling. Integration of such an on-chip thermometer into low-noise satellite front-end readout ASIC also imposes consumption optimization and the ability to operate in the space environment. First, an analytical study has to establish the trade-offs to be considered between technology, supply voltage, consumption and sensitivity. A CMOS version and a BiCMOS version will be designed during the thesis and characterized in a temperature range from -20 ° C to + 80 ° C.
  • Asynchronous correction for triple modular redundancy: this second part, mainly digital, focuses on changes in memory state caused by ionizing particles (Single-Event Upset - SEU). Triple Modular Redundancy (TMR) and Self-Restoring Logic (SRL) will be studied. The specificity of this work will be related to the study/research for a correction architecture without clocks, able to detect and correct a change of state asynchronously, where the existing SRLs require up to 3 clocks. A clock-less correction allows the integration of this function on low-noise front-end readout ASICs, for which, the clock signals can be inhibited. Particular attention will also be given to the stability of the correction. The testability by simulation and measurements will also have to be considered to emulate the changes of state of memories onboard a satellite. Radiation tests in front of a cyclotron are envisaged during the PhD to validate the self-correction techniques.
ASICs fine thermometry and the implementation of clock-less self-correction on DAC and ADC registers are major challenges for onboard astronomical applications. These two technics increase the robustness and reliability of the space instruments in which the APC contributes. These challenges therefore constitute a rich and ambitious instrumental thesis subject that fits perfectly into the perspectives of instrument developments of the APC laboratory, in particular within the framework of the development of the readout chain of the X-IFU instrument for ATHENA space mission. Further the APC applications, these are also innovative subjects that meet current needs in the general field of microelectronics. The PhD student will have to have a strong skill in electronics, microelectronics and controlled systems. He will first establish a state of the art of “on-chip” thermometry techniques and mitigation of Single-Event Upset - SEU. For simulations and circuit design, he will use Cadence Virtuoso CAD tools. So, it is assumed that he has already had initial training on these tools. BiCMOS SiGe ST 130 nm technology will be preferred for the ASIC design. One to two runs of ASIC are considered during the thesis. The handling and adaptation of a thermal test bench have also to be considered. Participation in a radiation test campaign in a cyclotron is also planned. The results will lead to the drafting of detailed datasheets and publications in international peer-reviewed journals.



Damien PRELE






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